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In this paper, hardware implemented artificial neural networks (ANN's) capable of learning on silicon are considered. The ability to learn within a chip means that the network can fast adapt to varying conditions during the recall phase, i.e. can learn in operation. This is impossible in classical ANN's. Thinking about building such adaptive networks became realistic only recently due to advances in CMOS processes. An important and difficult task in hardware implementations of the ANN's is to find proper solutions for analog circuits that can play a role of basie network elements such as synapses, analog [ocal memories and activation Junction circuits. Concrete realizations of these circuits have been presented. The shown circuits were designed in the Institute of Telecommunication, ATR in Bydgoszcz, Poland. The performed experimental studies concern a prototype CMOS chip, fabricated by Nordic in the framework of EUROPRACTICE.
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Operational Program Digital Poland, 2014-2020, Measure 2.3: Digital accessibility and usefulness of public sector information; funds from the European Regional Development Fund and national co-financing from the state budget.
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Click the link below to view the content.https://www.ibspan.waw.pl/~alex/OZwRCIN/WA777_0_KS-2003-01-T33R05P07_Zastosowania informatyki i analizy systemowej w zarządzaniu * Modele, techniki i systemy zarządzania w projektach badawczych i celowych KBN * Sprzętowa realizacja adaptacyjnych sieci neuronowych_content.pdf